NXP Semiconductors /LPC43xx /TIMER0 /CCR

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Interpret as CCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CAP0RE 0 (DISABLED)CAP0FE 0 (DISABLED)CAP0I 0 (DISABLED)CAP1RE 0 (DISABLED)CAP1FE 0 (DISABLED)CAP1I 0 (DISABLED)CAP2RE 0 (DISABLED)CAP2FE 0 (DISABLED)CAP2I 0 (DISABLED)CAP3RE 0 (DISABLED)CAP3FE 0 (DISABLED)CAP3I 0RESERVED

CAP0FE=DISABLED, CAP0RE=DISABLED, CAP3FE=DISABLED, CAP1FE=DISABLED, CAP2FE=DISABLED, CAP1I=DISABLED, CAP3RE=DISABLED, CAP1RE=DISABLED, CAP2RE=DISABLED, CAP2I=DISABLED, CAP0I=DISABLED, CAP3I=DISABLED

Description

Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Fields

CAP0RE

Capture on CAPn.0 rising edge

0 (DISABLED): Disabled. This feature is disabled.

1 (LOW_TO_HIGH): Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.

CAP0FE

Capture on CAPn.0 falling edge

0 (DISABLED): Disabled. This feature is disabled.

1 (HIGH_TO_LOW): High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.

CAP0I

Interrupt on CAPn.0 event

0 (DISABLED): Disabled. This feature is disabled.

1 (LOAD): Load. A CR0 load due to a CAPn.0 event will generate an interrupt.

CAP1RE

Capture on CAPn.1 rising edge

0 (DISABLED): Disabled. This feature is disabled.

1 (LOW_TO_HIGH): Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.

CAP1FE

Capture on CAPn.1 falling edge

0 (DISABLED): Disabled. This feature is disabled.

1 (HIGH_TO_LOW): High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.

CAP1I

Interrupt on CAPn.1 event

0 (DISABLED): Disabled. This feature is disabled.

1 (LOAD): Load. A CR1 load due to a CAPn.1 event will generate an interrupt.

CAP2RE

Capture on CAPn.2 rising edge

0 (DISABLED): Disabled. This feature is disabled.

1 (LOW_TO_HIGH): Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC.

CAP2FE

Capture on CAPn.2 falling edge:

0 (DISABLED): Disabled. This feature is disabled.

1 (HIGH_TO_LOW): High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC.

CAP2I

Interrupt on CAPn.2 event

0 (DISABLED): Disabled. This feature is disabled.

1 (LOAD): Load. A CR2 load due to a CAPn.2 event will generate an interrupt.

CAP3RE

Capture on CAPn.3 rising edge

0 (DISABLED): Disabled. This feature is disabled.

1 (LOW_TO_HIGH): Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC.

CAP3FE

High to low. Capture on CAPn.3 falling edge

0 (DISABLED): Disabled. This feature is disabled.

1 (HIGH_TO_LOW): A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC.

CAP3I

Interrupt on CAPn.3 event:

0 (DISABLED): Disabled. This feature is disabled.

1 (LOAD): Load. A CR3 load due to a CAPn.3 event will generate an interrupt.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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